Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
u2|u9 31 0 0 0 32 0 0 0 0 0 0 0 0
u2|u8 31 0 0 0 32 0 0 0 0 0 0 0 0
u2|u7 3 0 0 0 2 0 0 0 0 0 0 0 0
u2|u6 6 0 0 0 2 0 0 0 0 0 0 0 0
u2|u5 3 0 0 0 1 0 0 0 0 0 0 0 0
u2|u4 3 0 0 0 1 0 0 0 0 0 0 0 0
u2|u10|u10 4 0 0 0 2 0 0 0 0 0 0 0 0
u2|u10 4 0 0 0 2 0 0 0 0 0 0 0 0
u2|u3 66 0 62 0 2 0 0 0 0 0 0 0 0
u2|u2 2 0 0 0 2 0 0 0 0 0 0 0 0
u2 30 0 0 0 1 0 0 0 0 0 0 0 0
u1|u5 30 0 4 0 28 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|ctrl 3 0 0 0 6 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Ures_reg 32 0 0 0 28 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Uaddl_2_n_0_n 62 0 0 0 31 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Uaddl_1_n_1_n 60 0 0 0 30 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Uaddl_1_n_0_n 60 0 0 0 30 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Uaddl_0_n_3_n 58 0 2 0 29 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Uaddl_0_n_2_n 58 0 2 0 29 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Uaddl_0_n_1_n 58 0 2 0 29 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Uaddl_0_n_0_n 58 0 2 0 29 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umtl_7_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umlu_7_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umtl_6_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umlu_6_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umtl_5_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umlu_5_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umtl_4_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umlu_4_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umtl_3_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umlu_3_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umtl_2_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umlu_2_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umtl_1_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umlu_1_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umtl_0_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Umlu_0_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Ucoef_7_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Ucoef_6_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Ucoef_5_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Ucoef_4_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Ucoef_3_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Ucoef_2_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Ucoef_1_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Ucoef_0_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|U_7_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|U_6_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|U_5_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|U_4_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|U_3_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|U_2_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|U_1_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|U_0_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_15_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_14_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_13_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_12_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_11_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_10_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_9_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_8_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_7_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_6_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_5_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_4_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_3_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_2_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_1_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|tdl_ff_0_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore|Udin 19 0 0 0 15 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|fircore 18 0 0 0 30 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|intf_ctrl 9 1 0 1 6 1 1 1 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|source 36 4 1 4 35 4 4 4 0 0 0 0 0
u1|u4|fir_lpf_ast_inst|sink 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u4|fir_lpf_ast_inst 21 0 0 0 32 0 0 0 0 0 0 0 0
u1|u4 21 1 0 1 32 1 1 1 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|ctrl 3 0 0 0 6 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Ures_reg 32 0 0 0 28 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Uaddl_2_n_0_n 62 0 0 0 31 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Uaddl_1_n_1_n 60 0 0 0 30 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Uaddl_1_n_0_n 60 0 0 0 30 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Uaddl_0_n_3_n 58 0 2 0 29 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Uaddl_0_n_2_n 58 0 2 0 29 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Uaddl_0_n_1_n 58 0 2 0 29 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Uaddl_0_n_0_n 58 0 2 0 29 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umtl_7_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umlu_7_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umtl_6_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umlu_6_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umtl_5_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umlu_5_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umtl_4_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umlu_4_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umtl_3_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umlu_3_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umtl_2_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umlu_2_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umtl_1_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umlu_1_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umtl_0_n 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Umlu_0_n 30 0 0 0 28 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Ucoef_7_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Ucoef_6_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Ucoef_5_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Ucoef_4_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Ucoef_3_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Ucoef_2_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Ucoef_1_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Ucoef_0_n 16 13 0 13 12 13 13 13 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|U_7_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|U_6_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|U_5_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|U_4_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|U_3_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|U_2_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|U_1_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|U_0_sym_add 32 0 0 0 16 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_15_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_14_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_13_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_12_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_11_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_10_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_9_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_8_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_7_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_6_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_5_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_4_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_3_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_2_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_1_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|tdl_ff_0_ch_0_n 18 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore|Udin 19 0 0 0 15 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|fircore 18 0 0 0 30 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|intf_ctrl 9 1 0 1 6 1 1 1 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|source 36 4 1 4 35 4 4 4 0 0 0 0 0
u1|u3|fir_lpf_ast_inst|sink 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u3|fir_lpf_ast_inst 21 0 0 0 32 0 0 0 0 0 0 0 0
u1|u3 21 0 0 0 32 0 0 0 0 0 0 0 0
u1|u2|lpm_mult_component|auto_generated 17 0 0 0 15 0 0 0 0 0 0 0 0
u1|u2 17 0 0 0 15 0 0 0 0 0 0 0 0
u1|u1|lpm_mult_component|auto_generated 17 0 0 0 15 0 0 0 0 0 0 0 0
u1|u1 17 0 0 0 15 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|ux710isdr 3 0 0 0 1 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|ux123 13 0 0 0 10 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|ux122 13 0 0 0 10 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|rot 44 0 0 0 20 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|ux0121 9 0 0 0 9 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|ux0120 9 0 0 0 9 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|sid2c 21 0 0 0 40 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|ux007 11 0 0 0 7 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|ux0219 32 1 17 1 16 1 1 1 0 0 0 0 0
u1|u0|nco_st_inst|ux002 23 0 0 0 15 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|ux001 3 0 0 0 5 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|ux000 0 0 0 0 0 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|ux003 67 0 0 0 32 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|tdl 6 0 0 0 3 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst|u011 15 0 12 0 3 0 0 0 0 0 0 0 0
u1|u0|nco_st_inst 67 0 0 0 21 0 0 0 0 0 0 0 0
u1|u0 67 33 0 33 21 33 33 33 0 0 0 0 0
u1 10 0 0 0 64 0 0 0 0 0 0 0 0