12 const uint8_t g_abyEDIDHeader[] = { 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00 };
14 #define EDID_WEEK_NOT_SPECIFIED (0x00) 15 #define EDID_WEEK_MODEL_YEAR (0xFF) // Valid for EDID 1.4 16 #define EDID_WEEK_MIN (1) 17 #define EDID_WEEK_MAX (54) 18 #define EDID_YEAR_MIN (0x10) 19 #define EDID_YEAR_BASE (1990) 21 #define EDID_INPUT_INTERFACE_DIGITAL (0x80) 23 #define EDID_INPUT_ANALOG_LEVEL_SHIFT (5) 24 #define EDID_INPUT_ANALOG_LEVEL_MASK (0x03) 25 #define EDID_INPUT_ANALOG_LEVEL_0700_0300 (0) 26 #define EDID_INPUT_ANALOG_LEVEL_0714_0286 (1) 27 #define EDID_INPUT_ANALOG_LEVEL_1000_0400 (2) 28 #define EDID_INPUT_ANALOG_LEVEL_0700_0000 (3) 30 #define EDID_INPUT_ANALOG_BLANK_SETUP_EXPECTED (0x10) 31 #define EDID_INPUT_ANALOG_SEPARATE_SYNC (0x08) 32 #define EDID_INPUT_ANALOG_COMPOSITE_SYNC (0x04) 33 #define EDID_INPUT_ANALOG_SYNC_ON_GREEN (0x02) 34 #define EDID_INPUT_ANALOG_SERRATION (0x01) 36 #define EDID_INPUT_DIGITAL_BIT_DEPTH_SHIFT (4) // Valid for EDID 1.4 37 #define EDID_INPUT_DIGITAL_BIT_DEPTH_MASK (0x07) 38 #define EDID_INPUT_DIGITAL_BIT_DEPTH_UNDEFINED (0) 39 #define EDID_INPUT_DIGITAL_BIT_DEPTH_6 (1) 40 #define EDID_INPUT_DIGITAL_BIT_DEPTH_8 (2) 41 #define EDID_INPUT_DIGITAL_BIT_DEPTH_10 (3) 42 #define EDID_INPUT_DIGITAL_BIT_DEPTH_12 (4) 43 #define EDID_INPUT_DIGITAL_BIT_DEPTH_14 (5) 44 #define EDID_INPUT_DIGITAL_BIT_DEPTH_16 (6) 46 #define EDID_INPUT_DIGITAL_INTERFACE_MASK (0x0F) // Valid for EDID 1.4 47 #define EDID_INPUT_DIGITAL_INTERFACE_UNDEFINED (0) 48 #define EDID_INPUT_DIGITAL_INTERFACE_DVI (1) 49 #define EDID_INPUT_DIGITAL_INTERFACE_HDMI_A (2) 50 #define EDID_INPUT_DIGITAL_INTERFACE_HDMI_B (3) 51 #define EDID_INPUT_DIGITAL_INTERFACE_MDDI (4) 52 #define EDID_INPUT_DIGITAL_INTERFACE_DP (5) 54 #define EDID_FEATURE_DFP1X_COMPATIBLE (0x01) // Valid for EDID 1.3 56 #define EDID_HORZ_PORTRAIT_AR (0x00) // Valid for EDID 1.4 57 #define EDID_VERT_LANDSCAPE_AR (0x00) // Valid for EDID 1.4 58 #define EDID_HORZ_FROM_LANDSCAPE_AR(ar) (round((ar) * 100.0f) - 99) 59 #define EDID_HORZ_TO_LANDSCAPE_AR(val) (((val) + 99) / 100.0f) 60 #define EDID_VERT_FROM_PORTRAIT_AR(ar) (round(100.0f / (ar)) - 99) 61 #define EDID_VERT_TO_PORTRAIT_AR(val) (100.0f / ((val) + 99)) 63 #define EDID_DTC_FROM_GAMMA(gamma) (round((gamma) * 100.0f) - 100) 64 #define EDID_DTC_TO_GAMMA(val) (((val) + 100) / 100.0f) 66 #define EDID_FEATURE_STANDBY (0x80) 67 #define EDID_FEATURE_SUSPEND (0x40) 68 #define EDID_FEATURE_ACTIVE_OFF (0x20) 70 #define EDID_FEATURE_DISPLAY_COLOR_TYPE_SHIFT (3) 71 #define EDID_FEATURE_DISPLAY_COLOR_TYPE_MASK (0x03) 72 #define EDID_FEATURE_COLOR_TYPE_A_MONO (0) 73 #define EDID_FEATURE_COLOR_TYPE_A_RGB (1) 74 #define EDID_FEATURE_COLOR_TYPE_A_NON_RGB (2) 75 #define EDID_FEATURE_COLOR_TYPE_A_UNDEFINED (3) 76 #define EDID_FEATURE_COLOR_TYPE_D_RGB444 (0) // Valid for EDID 1.4 when EDID_INPUT_INTERFACE_DIGITAL 77 #define EDID_FEATURE_COLOR_TYPE_D_RGBYUV444 (1) 78 #define EDID_FEATURE_COLOR_TYPE_D_RGB444_YUV422 (2) 79 #define EDID_FEATURE_COLOR_TYPE_D_RGB444_YUV444_422 (3) 81 #define EDID_FEATURE_DEFAULT_SRGB (0x04) 82 #define EDID_FEATURE_PREFERRED_TIMING_MODE (0x02) // Must set for EDID 1.3 83 #define EDID_FEATURE_DEFAULT_GTF (0x01) // Valid for EDID 1.3 84 #define EDID_FEATURE_CONTINUOUS_FREQUENCY (0x01) // Valid for EDID 1.4 86 #define EDID_EST_TIMING_I_720x400_70 (0x80) 87 #define EDID_EST_TIMING_I_720x400_88 (0x40) 88 #define EDID_EST_TIMING_I_640x480_60 (0x20) 89 #define EDID_EST_TIMING_I_640x480_67 (0x10) 90 #define EDID_EST_TIMING_I_640x480_72 (0x08) 91 #define EDID_EST_TIMING_I_640x480_75 (0x04) 92 #define EDID_EST_TIMING_I_800x600_56 (0x02) 93 #define EDID_EST_TIMING_I_800x600_60 (0x01) 95 #define EDID_EST_TIMING_II_800x600_72 (0x80) 96 #define EDID_EST_TIMING_II_800x600_75 (0x40) 97 #define EDID_EST_TIMING_II_832x624_75 (0x20) 98 #define EDID_EST_TIMING_II_1024x768_87i (0x10) 99 #define EDID_EST_TIMING_II_1024x768_60 (0x08) 100 #define EDID_EST_TIMING_II_1024x768_70 (0x04) 101 #define EDID_EST_TIMING_II_1024x768_75 (0x02) 102 #define EDID_EST_TIMING_II_1280x1024_75 (0x01) 104 #define EDID_RES_TIMING_1152x870_75 (0x80) 106 #define EDID_STD_TIMING_UNUSED (0x0101) 107 #define EDID_STD_TIMING_AR_16_10 (0) 108 #define EDID_STD_TIMING_AR_4_3 (1) 109 #define EDID_STD_TIMING_AR_5_4 (2) 110 #define EDID_STD_TIMING_AR_16_9 (3) 111 #define EDID_STD_TIMING_GET_AR(w) ((w) >> 14) 112 #define EDID_STD_TIMING_GET_REFRESH(w) (((w) >> 8) & 0x3F) // 60-123 113 #define EDID_STD_TIMING_GET_H_ACTIVE(w) ((((w) & 0xFF) + 31) * 8) // 256-2288 114 #define EDID_STD_TIMING_PACK(h, refresh, ar) (((h) / 8 - 31) | (((refresh) - 60) << 8) | ((ar) << 14)) 118 uint8_t abyHeader[8];
120 uint8_t abyManufacturerName[2];
121 uint16_t wProductCode;
122 uint32_t dwSerialNumber;
129 uint8_t byVideoInputDefinision;
130 uint8_t byHorizontalSize;
131 uint8_t byVerticalSize;
132 uint8_t byDisplayXferCharacteristics;
133 uint8_t byFeatureSupport;
135 uint8_t byRedGreenLSB;
136 uint8_t byBlueWhiteLSB;
146 uint8_t byEstablishedTimingsI;
147 uint8_t byEstablishedTimingsII;
148 uint8_t byManufacturerReservedTimings;
150 uint16_t abyStandardTimings[8];
152 uint8_t abyPreferredTimingMode[18];
153 uint8_t abyDTD2OrDisplayDescriptor[18];
154 uint8_t abyDTD3OrDisplayDescriptor[18];
155 uint8_t abyDTD4OrDisplayDescriptor[18];
157 uint8_t byExtensionBlockCount;
161 inline void EDID_DecodeISAPnPID(
char * pszName,
const uint8_t * pbyID) {
162 uint16_t wID = (pbyID[0] << 8) | pbyID[1];
164 pszName[2] = ((wID >> 0) & 0x1F) +
'A' - 1;
165 pszName[1] = ((wID >> 5) & 0x1F) +
'A' - 1;
166 pszName[0] = ((wID >> 10) & 0x1F) +
'A' - 1;
169 inline void EDID_EncodeISAPnPID(
const char * pszName, uint8_t * pbyID) {
171 wID |= (((pszName[0] -
'A') + 1) & 0x1F) << 10;
172 wID |= (((pszName[1] -
'A') + 1) & 0x1F) << 5;
173 wID |= (((pszName[2] -
'A') + 1) & 0x1F) << 0;
175 pbyID[0] = (wID >> 8);
176 pbyID[1] = (wID & 0xFF);
179 inline bool EDID_VerifyBlock(uint8_t * pbyEDIDBlock)
182 for (
int i = 0; i < 128; i++)
183 bySum += *pbyEDIDBlock++;
188 inline uint8_t EDID_CalcCheckSum(
const uint8_t * pbyEDIDBlock)
191 for (
int i = 0; i < 127; i++)
192 bySum += *pbyEDIDBlock++;
199 #define EDID_DTD_TIMING_FLAGS_INTERLACED (0x80) 201 #define EDID_DTD_TIMING_FLAGS_STEREO_SUPPORT(val) ((((val) >> 4) && 0x06) | ((val) & 0x01)) 202 #define EDID_DTD_TIMING_FLAGS_STEREO_NONE_0 (0x00) 203 #define EDID_DTD_TIMING_FLAGS_STEREO_NONE_1 (0x01) 204 #define EDID_DTD_TIMING_FLAGS_STEREO_FS_R (0x02) 205 #define EDID_DTD_TIMING_FLAGS_STEREO_FS_L (0x04) 206 #define EDID_DTD_TIMING_FLAGS_STEREO_2WAY_R (0x03) 207 #define EDID_DTD_TIMING_FLAGS_STEREO_2WAY_L (0x05) 208 #define EDID_DTD_TIMING_FLAGS_STEREO_4WAY (0x06) 209 #define EDID_DTD_TIMING_FLAGS_STEREO_SIDE_BY_SIDE (0x07) 211 #define EDID_DTD_TIMING_FLAGS_SYNC_DIGITAL_SYNC (0x08) 212 #define EDID_DTD_TIMING_FLAGS_SYNC_A_BIPOLAR (0x04) 213 #define EDID_DTD_TIMING_FLAGS_SYNC_A_ON_RGB (0x01) 214 #define EDID_DTD_TIMING_FLAGS_SYNC_D_SEPARATE (0x04) 215 #define EDID_DTD_TIMING_FLAGS_SYNC_D_POSITIVE_VS (0x02) // Valid for separate digital sync 216 #define EDID_DTD_TIMING_FLAGS_SYNC_D_POSITIVE_HS (0x01) // Valid for separate digital sync 217 #define EDID_DTD_TIMING_FLAGS_SYNC_SERRATIONS (0x02) // Valid for analog or composite digital sync 219 #define EDID_DTD_TIMING_FLAGS_PACK(i, sync, stereo) (((i) ? 0x80 : 0x00) | (sync) | ((stereo) & 0x01) | (((stereo) & 0x06) << 4)) 222 uint16_t wPixelClockFreq;
225 uint8_t byHAddrBlankMSB;
228 uint8_t byVAddrBlankMSB;
229 uint8_t byHFrontPorchLSB;
230 uint8_t byHSyncPulseWidthLSB;
231 uint8_t byVFrontPorchSyncPulseWidthLSB;
232 uint8_t byFrontPorchSyncPulseWidthMSB;
233 uint8_t byHImageSizeLSB;
234 uint8_t byVImageSizeLSB;
235 uint8_t byImageSizeMSB;
236 uint8_t byHBorderPixels;
237 uint8_t byVBorderPixels;
241 #define EDID_DISPLAY_TAG_SN (0xFF) 242 #define EDID_DISPLAY_TAG_ASCII (0xFE) 243 #define EDID_DISPLAY_TAG_RANGE_LIMITS (0xFD) 244 #define EDID_DISPLAY_TAG_PRODUCT_NAME (0xFC) 245 #define EDID_DISPLAY_TAG_COLOR_POINT_DATA (0xFB) 246 #define EDID_DISPLAY_TAG_STANDARD_TIMING_IDS (0xFA) 247 #define EDID_DISPLAY_TAG_DCM_DATA (0xF9) 248 #define EDID_DISPLAY_TAG_CVT3_BYTE_TIMING_CODES (0xF8) 249 #define EDID_DISPLAY_TAG_EST_TIMINGS_III (0xF7) 250 #define EDID_DISPLAY_TAG_DUMMY (0x10) 251 #define EDID_DISPLAY_TAG_MANUFACTURER_MAX (0x0F) 252 #define EDID_DISPLAY_TAG_MANUFACTURER_MIN (0x00) 257 uint8_t byDisplayDescTagNumber;
262 #define EDID_DISPLAY_RANGE_MIN_VERT_OFFSET_255Hz (0x01) 263 #define EDID_DISPLAY_RANGE_MAX_VERT_OFFSET_255Hz (0x02) 264 #define EDID_DISPLAY_RANGE_MIN_HORZ_OFFSET_255KHz (0x04) 265 #define EDID_DISPLAY_RANGE_MAX_HORZ_OFFSET_255KHz (0x08) 267 #define EDID_DISPLAY_RANGE_DEFAULT_GTF (0x00) // EDID_FEATURE_CONTINUOUS_FREQUENCY must be set for this mode 268 #define EDID_DISPLAY_RANGE_RANGE_LIMIT_ONLY (0x01) // Valid in 1.4 269 #define EDID_DISPLAY_RANGE_SECONDARY_GTF (0x02) // EDID_FEATURE_CONTINUOUS_FREQUENCY must be set for this mode 270 #define EDID_DISPLAY_RANGE_CVT (0x04) // Valid in 1.4, EDID_FEATURE_CONTINUOUS_FREQUENCY must be set for this mode 272 const uint8_t g_abyEDIDRangeLimitVideoTimingDataEmpty[7] = { 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
278 uint8_t byDisplayDescTagNumber;
279 uint8_t byRangeLimitOffsets;
280 uint8_t byMinVertRate;
281 uint8_t byMaxVertRate;
282 uint8_t byMinHorzRate;
283 uint8_t byMaxHorzRate;
284 uint8_t byMaxPixelClockFreq;
285 uint8_t byVideoTimingSupportFlags;
286 uint8_t abyVideoTimingData[7];
289 inline PEDID_DISPLAY_RANGE_LIMITS_DESC FindDisplayRangeLimitDesc(PEDID_BASE_BLOCK pBaseBlock) {
290 PEDID_DISPLAY_RANGE_LIMITS_DESC pDisplayRangeDesc = (PEDID_DISPLAY_RANGE_LIMITS_DESC)pBaseBlock->abyDTD2OrDisplayDescriptor;
292 for (
int i = 0; i < 3; i++) {
293 if (pDisplayRangeDesc->wZero == 0
294 && pDisplayRangeDesc->byZero == 0
295 && pDisplayRangeDesc->byDisplayDescTagNumber == EDID_DISPLAY_TAG_RANGE_LIMITS) {
296 return pDisplayRangeDesc;
307 uint8_t byStartBreakFreq;
314 #define EDID_DISPLAY_RANGE_CVT_SUPPORTED_AR_4_3 (0x80) 315 #define EDID_DISPLAY_RANGE_CVT_SUPPORTED_AR_16_9 (0x40) 316 #define EDID_DISPLAY_RANGE_CVT_SUPPORTED_AR_16_10 (0x20) 317 #define EDID_DISPLAY_RANGE_CVT_SUPPORTED_AR_5_4 (0x10) 318 #define EDID_DISPLAY_RANGE_CVT_SUPPORTED_AR_15_9 (0x08) 319 #define EDID_DISPLAY_RANGE_CVT_PREFERED_AR_4_3 (0) 320 #define EDID_DISPLAY_RANGE_CVT_PREFERED_AR_16_9 (1) 321 #define EDID_DISPLAY_RANGE_CVT_PREFERED_AR_16_10 (2) 322 #define EDID_DISPLAY_RANGE_CVT_PREFERED_AR_5_4 (3) 323 #define EDID_DISPLAY_RANGE_CVT_PREFERED_AR_15_9 (4) 324 #define EDID_DISPLAY_RANGE_CVT_REDUCED_BLANKING (0x10) 325 #define EDID_DISPLAY_RANGE_CVT_STANDARD_BLANKING (0x08) 326 #define EDID_DISPLAY_RANGE_CVT_HORZ_SHRINK (0x80) 327 #define EDID_DISPLAY_RANGE_CVT_HORZ_STRETCH (0x40) 328 #define EDID_DISPLAY_RANGE_CVT_VERT_SHRINK (0x20) 329 #define EDID_DISPLAY_RANGE_CVT_VERT_STRETCH (0x10) 333 uint8_t byMaxHActiveMSB : 2;
334 uint8_t byAdditionalPixelClockPrecision : 6;
335 uint8_t byMaxHActiveLSB;
336 uint8_t bySupportedAR;
337 uint8_t byReserved : 3;
338 uint8_t byCVTBlankingSupport : 2;
339 uint8_t byPreferedAR : 3;
340 uint8_t byDisplayScalingSupport;
341 uint8_t byPreferedVertRefreshRate;
347 uint8_t byDisplayDescTagNumber;
349 uint16_t awStandardTimings[6];
353 #define EDID_EST_TIMING_III_1_640x350_85 (0x80) 354 #define EDID_EST_TIMING_III_1_640x400_85 (0x40) 355 #define EDID_EST_TIMING_III_1_720x400_85 (0x20) 356 #define EDID_EST_TIMING_III_1_640x480_85 (0x10) 357 #define EDID_EST_TIMING_III_1_848x480_60 (0x08) 358 #define EDID_EST_TIMING_III_1_800x600_85 (0x04) 359 #define EDID_EST_TIMING_III_1_1024x768_85 (0x02) 360 #define EDID_EST_TIMING_III_1_1152x864_75 (0x01) 362 #define EDID_EST_TIMING_III_2_1280x768_60_RB (0x80) 363 #define EDID_EST_TIMING_III_2_1280x768_60 (0x40) 364 #define EDID_EST_TIMING_III_2_1280x768_75 (0x20) 365 #define EDID_EST_TIMING_III_2_1280x768_85 (0x10) 366 #define EDID_EST_TIMING_III_2_1280x960_60 (0x08) 367 #define EDID_EST_TIMING_III_2_1280x960_85 (0x04) 368 #define EDID_EST_TIMING_III_2_1280x1024_60 (0x02) 369 #define EDID_EST_TIMING_III_2_1280x1024_85 (0x01) 371 #define EDID_EST_TIMING_III_3_1360x768_60 (0x80) 372 #define EDID_EST_TIMING_III_3_1440x900_60_RB (0x40) 373 #define EDID_EST_TIMING_III_3_1440x900_60 (0x20) 374 #define EDID_EST_TIMING_III_3_1440x900_75 (0x10) 375 #define EDID_EST_TIMING_III_3_1440x900_85 (0x08) 376 #define EDID_EST_TIMING_III_3_1400x1050_60_RB (0x04) 377 #define EDID_EST_TIMING_III_3_1400x1050_60 (0x02) 378 #define EDID_EST_TIMING_III_3_1400x1050_75 (0x01) 380 #define EDID_EST_TIMING_III_4_1400x1050_85 (0x80) 381 #define EDID_EST_TIMING_III_4_1680x1050_60_RB (0x40) 382 #define EDID_EST_TIMING_III_4_1680x1050_60 (0x20) 383 #define EDID_EST_TIMING_III_4_1680x1050_75 (0x10) 384 #define EDID_EST_TIMING_III_4_1680x1050_85 (0x08) 385 #define EDID_EST_TIMING_III_4_1600x1200_60 (0x04) 386 #define EDID_EST_TIMING_III_4_1600x1200_65 (0x02) 387 #define EDID_EST_TIMING_III_4_1600x1200_70 (0x01) 389 #define EDID_EST_TIMING_III_5_1600x1200_75 (0x80) 390 #define EDID_EST_TIMING_III_5_1600x1200_85 (0x40) 391 #define EDID_EST_TIMING_III_5_1792x1344_60 (0x20) 392 #define EDID_EST_TIMING_III_5_1792x1344_75 (0x10) 393 #define EDID_EST_TIMING_III_5_1856x1392_60 (0x08) 394 #define EDID_EST_TIMING_III_5_1856x1392_75 (0x04) 395 #define EDID_EST_TIMING_III_5_1920x1200_60_RB (0x02) 396 #define EDID_EST_TIMING_III_5_1920x1200_60 (0x01) 398 #define EDID_EST_TIMING_III_6_1920x1200_75 (0x80) 399 #define EDID_EST_TIMING_III_6_1920x1200_85 (0x40) 400 #define EDID_EST_TIMING_III_6_1920x1440_60 (0x20) 401 #define EDID_EST_TIMING_III_6_1920x1440_75 (0x10) 406 uint8_t byDisplayDescTagNumber;
409 uint8_t byEstTimingIII_1;
410 uint8_t byEstTimingIII_2;
411 uint8_t byEstTimingIII_3;
412 uint8_t byEstTimingIII_4;
413 uint8_t byEstTimingIII_5;
414 uint8_t byEstTimingIII_6;
415 uint8_t abyReserved[6];
418 #define EDID_BLOCK_TAG_UNUSED (0x00) 419 #define EDID_BLOCK_TAG_CEA_EXT (0x02) 420 #define EDID_BLOCK_TAG_VTB_EXT (0x10) 421 #define EDID_BLOCK_TAG_DI_EXT (0x40) 422 #define EDID_BLOCK_TAG_LS_EXT (0x50) 423 #define EDID_BLOCK_TAG_DPVL_EXT (0x60) 424 #define EDID_BLOCK_TAG_BLOCK_MAP (0xF0) 425 #define EDID_BLOCK_TAG_MANUFACTURER (0xFF) 428 uint8_t byBlockTagNumber;
429 uint8_t byRevisionNumber;
430 uint8_t abyData[125];
435 uint8_t byMapBlockTagNumber;
436 uint8_t abyBlockTagNumbers[126];
440 #define EDID_CEA_FLAG_UNDERSCAN (0x08) 441 #define EDID_CEA_FLAG_BASIC_AUDIO (0x04) 442 #define EDID_CEA_FLAG_YCbCr444 (0x02) 443 #define EDID_CEA_FLAG_YCbCr422 (0x01) 445 #define EDID_CEA_PADDING_DATA (0x00) 448 uint8_t byBlockTagNumber;
449 uint8_t byRevisionNumber;
450 uint8_t byDetailedTimingDescOffset;
451 uint8_t byNumNativeDTDs : 4;
458 #define EDID_CEA_BLOCK_TAG_AUDIO (0x01) 459 #define EDID_CEA_BLOCK_TAG_VIDEO (0x02) 460 #define EDID_CEA_BLOCK_TAG_VENDOR_SPECIFIC (0x03) 461 #define EDID_CEA_BLOCK_TAG_SPEAKER_ALLOCATION (0x04) 462 #define EDID_CEA_BLOCK_TAG_VESA_DISPLAY_XFER (0x05) 463 #define EDID_CEA_BLOCK_TAG_USE_EXTENDED_TAG (0x07) 466 uint8_t byDataLength : 5;
467 uint8_t byTagCode : 3;
471 #define EDID_CEA_BLOCK_EXT_TAG_VIDEO_CAPABILITY (00) 472 #define EDID_CEA_BLOCK_EXT_TAG_VENDOR_SPECIFIC_VIDEO (01) 473 #define EDID_CEA_BLOCK_EXT_TAG_VESA_DISPLAY_DEVICE (02) 474 #define EDID_CEA_BLOCK_EXT_TAG_VESA_VIDEO_TIMING (03) 475 #define EDID_CEA_BLOCK_EXT_TAG_HDMI_VIDEO (04) 476 #define EDID_CEA_BLOCK_EXT_TAG_COLORIMETRY (05) 477 #define EDID_CEA_BLOCK_EXT_TAG_VIDEO_FORMAT_PREFERENCE (13) 478 #define EDID_CEA_BLOCK_EXT_TAG_YUV420_VIDEO (14) 479 #define EDID_CEA_BLOCK_EXT_TAG_YUV420_CAPABILITY_MAP (15) 480 #define EDID_CEA_BLOCK_EXT_TAG_VENDOR_SPECIFIC_AUDIO (17) 481 #define EDID_CEA_BLOCK_EXT_TAG_HDMI_AUDIO (18) 482 #define EDID_CEA_BLOCK_EXT_TAG_INFO_FRAME (32) 485 uint8_t byDataLength : 5;
486 uint8_t byTagCode : 3;
487 uint8_t byExtendedTagCode;
491 inline PEDID_CEA_DATA_BLOCK_HEADER EDID_FindCEAGetFirstDataBlock(PEDID_CEA_EXT_BLOCK_HEADER pCEAExt,
int& cbTotalBlockSize) {
492 cbTotalBlockSize = pCEAExt->byDetailedTimingDescOffset - 4;
493 if (cbTotalBlockSize <= 0)
496 PEDID_CEA_DATA_BLOCK_HEADER pBlockHdr = (PEDID_CEA_DATA_BLOCK_HEADER)(pCEAExt + 1);
497 if (cbTotalBlockSize < (pBlockHdr->byDataLength + 1))
503 inline PEDID_CEA_DATA_BLOCK_HEADER EDID_FindCEAGetNextDataBlock(PEDID_CEA_DATA_BLOCK_HEADER pDataBlock,
int& cbTotalBlockSize) {
504 uint8_t * pbyData = (uint8_t *)pDataBlock + pDataBlock->byDataLength + 1;
505 cbTotalBlockSize -= pDataBlock->byDataLength + 1;
506 if (cbTotalBlockSize <= 0)
509 PEDID_CEA_DATA_BLOCK_HEADER pBlockHdr = (PEDID_CEA_DATA_BLOCK_HEADER)pbyData;
510 if (cbTotalBlockSize < (pBlockHdr->byDataLength + 1))
516 inline PEDID_CEA_DATA_BLOCK_HEADER EDID_FindVSDB(PEDID_CEA_EXT_BLOCK_HEADER pCEAExt,
const uint8_t * pbyIEEE_OUI) {
517 int cbTotalBlockSize;
518 PEDID_CEA_DATA_BLOCK_HEADER pHdr = EDID_FindCEAGetFirstDataBlock(pCEAExt, cbTotalBlockSize);
521 if (pHdr->byTagCode == EDID_CEA_BLOCK_TAG_VENDOR_SPECIFIC
522 && pHdr->byDataLength >= 3) {
523 if (memcmp(pHdr + 1, pbyIEEE_OUI, 3) == 0)
527 pHdr = EDID_FindCEAGetNextDataBlock(pHdr, cbTotalBlockSize);
533 inline int EDID_GetCEADetailedTimingCount(PEDID_CEA_EXT_BLOCK_HEADER pCEAExt) {
534 int cbMaxDTDs = 127 - pCEAExt->byDetailedTimingDescOffset;
535 int cMaxDTDs = cbMaxDTDs / 18;
537 PEDID_DETAILED_TIMING_DESC pDTD = (PEDID_DETAILED_TIMING_DESC)((uint8_t *)pCEAExt + pCEAExt->byDetailedTimingDescOffset);
540 while (cDTDs < cMaxDTDs) {
541 if (pDTD->wPixelClockFreq == 0)
549 inline void EDID_RemoveCEADataBlock(PEDID_CEA_EXT_BLOCK_HEADER pCEAExt, PEDID_CEA_DATA_BLOCK_HEADER pDataBlock) {
550 int cbDataBlock = pDataBlock->byDataLength + 1;
552 uint8_t * pbyStart = (uint8_t *)pCEAExt;
553 uint8_t * pbyClear = (pbyStart + 127) - cbDataBlock;
554 uint8_t * pbyBlock = (uint8_t *)pDataBlock;
555 uint8_t * pbyNextBlock = pbyBlock + cbDataBlock;
556 int cbMove = 127 - (int)(pbyNextBlock - pbyStart);
558 memmove(pbyBlock, pbyNextBlock, cbMove);
559 memset(pbyClear, 0, cbDataBlock);
561 pCEAExt->byDetailedTimingDescOffset -= cbDataBlock;
564 inline bool EDID_InsertCEADataBlock(PEDID_CEA_EXT_BLOCK_HEADER pCEAExt, PEDID_CEA_DATA_BLOCK_HEADER pDataBlockPos, PEDID_CEA_DATA_BLOCK_HEADER pDataBlock) {
565 int cbBlock = (pDataBlock->byDataLength + 1);
566 int cDTDs = EDID_GetCEADetailedTimingCount(pCEAExt);
568 int cbPrevEnd = pCEAExt->byDetailedTimingDescOffset + cbDTDs;
569 int cbNewEnd = cbPrevEnd + cbBlock;
573 uint8_t * pbyStart = (uint8_t *)pCEAExt;
574 uint8_t * pbyPos = (pDataBlockPos == NULL) ? (uint8_t *)(pCEAExt + 1) : (uint8_t *)pDataBlockPos;
576 int cbMove = cbPrevEnd - (int)(pbyPos - pbyStart);
577 memmove(pbyPos + (pDataBlock->byDataLength + 1), pbyPos, cbMove);
578 memcpy(pbyPos, pDataBlock, cbBlock);
579 pCEAExt->byDetailedTimingDescOffset += cbBlock;
585 #define EDID_CEA_SVD_MAX_NUM (31) 586 #define EDID_CEA_SVD_FROM_VIC(native, vic) ((vic) <= 64 ? ((vic) | ((native) ? 0x80 : 0x00)) : (vic)) 587 #define EDIA_CEA_SVD_TO_VIC(svd) (((svd) & 0x7F) <= 64 ? ((svd) & 0x7F) : svd) 590 #define EDID_CEA_SAD_MAX_NUM (10) 592 #define EDID_CEA_SAD_FORMAT_LPCM (1) 593 #define EDID_CEA_SAD_FORMAT_AC3 (2) 594 #define EDID_CEA_SAD_FORMAT_MPEG1 (3) 595 #define EDID_CEA_SAD_FORMAT_MP3 (4) 596 #define EDID_CEA_SAD_FORMAT_MPEG2 (5) 597 #define EDID_CEA_SAD_FORMAT_AAC_LC (6) 598 #define EDID_CEA_SAD_FORMAT_DTS (7) 599 #define EDID_CEA_SAD_FORMAT_ATRAC (8) 600 #define EDID_CEA_SAD_FORMAT_ONE_BIT (9) 601 #define EDID_CEA_SAD_FORMAT_ENHANCED_AC3 (10) 602 #define EDID_CEA_SAD_FORMAT_DTS_HD (11) 603 #define EDID_CEA_SAD_FORMAT_MAT (12) 604 #define EDID_CEA_SAD_FORMAT_DST (13) 605 #define EDID_CEA_SAD_FORMAT_WMA_PRO (14) 606 #define EDID_CEA_SAD_FORMAT_EXTENSION (15) 608 #define EDID_CEA_SAD_SAMPLE_RATE_32K (0x01) 609 #define EDID_CEA_SAD_SAMPLE_RATE_44K1 (0x02) 610 #define EDID_CEA_SAD_SAMPLE_RATE_48K (0x04) 611 #define EDID_CEA_SAD_SAMPLE_RATE_88K2 (0x08) 612 #define EDID_CEA_SAD_SAMPLE_RATE_96K (0x10) 613 #define EDID_CEA_SAD_SAMPLE_RATE_176K4 (0x20) 614 #define EDID_CEA_SAD_SAMPLE_RATE_192K (0x40) 616 #define EDID_CEA_SAD_LPCM_BITS_16 (0x01) 617 #define EDID_CEA_SAD_LPCM_BITS_20 (0x02) 618 #define EDID_CEA_SAD_LPCM_BITS_24 (0x04) 620 #define EDID_CEA_SAD_WMA_PRO_PROFILE_MASK (0x07) 622 #define EDID_CEA_SAD_EXT_FORMAT_SHIFT (3) 623 #define EDID_CEA_SAD_EXT_FORMAT_MASK (0x1F) 624 #define EDID_CEA_SAD_EXT_FORMAT_DRA (0x00) 625 #define EDID_CEA_SAD_EXT_FORMAT_MPEG4_HE_AAC (0x04) 626 #define EDID_CEA_SAD_EXT_FORMAT_MPEG4_HE_AAC_V2 (0x05) 627 #define EDID_CEA_SAD_EXT_FORMAT_MPEG4_AAC_LC (0x06) 628 #define EDID_CEA_SAD_EXT_FORMAT_MPEG4_HE_AAC_MPS (0x08) 629 #define EDID_CEA_SAD_EXT_FORMAT_MPEG4_AAC_LC_MPS (0x10) 630 #define EDID_CEA_SAD_EXT_AAC_1024_TL (0x04) // Valid for 4-6, 8, 10 631 #define EDID_CEA_SAD_EXT_AAC_960_TL (0x02) // Valid for 4-6, 8, 10 632 #define EDID_CEA_SAD_EXT_AAC_MPS_L (0x01) // Valid for 8, 10 635 uint8_t byMaxNumChannelsMinusOne : 3;
636 uint8_t byAudioFormatCode : 4;
637 uint8_t byReserved1 : 1;
638 uint8_t bySampleRateSupported;
639 uint8_t byFormatRelatedData;
644 #define EDID_CEA_SPEAKER_1_FLW_FRW (0x80) 645 #define EDID_CEA_SPEAKER_1_RLC_RRC (0x40) 646 #define EDID_CEA_SPEAKER_1_FLC_FRC (0x20) 647 #define EDID_CEA_SPEAKER_1_RC (0x10) 648 #define EDID_CEA_SPEAKER_1_RL_RR (0x08) 649 #define EDID_CEA_SPEAKER_1_FC (0x04) 650 #define EDID_CEA_SPEAKER_1_LFE (0x02) 651 #define EDID_CEA_SPEAKER_1_FL_FR (0x01) 653 #define EDID_CEA_SPEAKER_2_FCH (0x04) 654 #define EDID_CEA_SPEAKER_2_TC (0x02) 655 #define EDID_CEA_SPEAKER_2_FLH_FRH (0x01) 664 #define EDID_CEA_COLORIMETRY_xvYCC601 (0x80) 665 #define EDID_CEA_COLORIMETRY_xvYCC709 (0x40) 666 #define EDID_CEA_COLORIMETRY_sYCC601 (0x20) 667 #define EDID_CEA_COLORIMETRY_ADOBE_YCC601 (0x10) 668 #define EDID_CEA_COLORIMETRY_ADOBE_RGB (0x08) 669 #define EDID_CEA_COLORIMETRY_BT2020_CYCC (0x04) 670 #define EDID_CEA_COLORIMETRY_BT2020_YCC (0x02) 671 #define EDID_CEA_COLORIMETRY_BT2020_RGB (0x01) 674 uint8_t byColorimetry;
675 uint8_t byFutureMetaData;
679 #define EDID_CEA_VIDEO_CAPABILITY_CE_SCAN_SHIFT (0) 680 #define EDID_CEA_VIDEO_CAPABILITY_IT_SCAN_SHIFT (2) 681 #define EDID_CEA_VIDEO_CAPABILITY_PT_SCAN_SHIFT (4) 682 #define EDID_CEA_VIDEO_CAPABILITY_SCAN_MASK (3) 683 #define EDID_CEA_VIDEO_CAPABILITY_SCAN_UNSUPPORTED (0) 684 #define EDID_CEA_VIDEO_CAPABILITY_SCAN_OVERSCANNED (1) 685 #define EDID_CEA_VIDEO_CAPABILITY_SCAN_UNDERSCANNED (2) 686 #define EDID_CEA_VIDEO_CAPABILITY_SCAN_BOTH_SUPPORTED (3) 687 #define EDID_CEA_VIDEO_CAPABILITY_QYCC_SELECTABLE (0x80) 688 #define EDID_CEA_VIDEO_CAPABILITY_QRGB_SELECTABLE (0x40) 691 #define EDID_CEA_SVR_MAX_NUM (31) 692 #define EDID_CEA_SVR_DTD_INDEX (0x80) 697 const uint8_t g_abyHDMI_FORUM[3] = { 0xD8, 0x5D, 0xC4 };
699 #define EDID_HDMI_FORUM_FLAG_1_SCDC_PRESENT (0x80) 700 #define EDID_HDMI_FORUM_FLAG_1_RR_CAPABLE (0x40) 701 #define EDID_HDMI_FORUM_FLAG_1_LTE_340M_SCRAMBLE (0x08) 702 #define EDID_HDMI_FORUM_FLAG_1_INDEPENDENT_VIEW (0x04) 703 #define EDID_HDMI_FORUM_FLAG_1_DUAL_VIEW (0x02) 704 #define EDID_HDMI_FORUM_FLAG_1_3D_OSD_DISPARITY (0x01) 706 #define EDID_HDMI_FORUM_FLAG_2_DC_48BIT_420 (0x04) 707 #define EDID_HDMI_FORUM_FLAG_2_DC_36BIT_420 (0x02) 708 #define EDID_HDMI_FORUM_FLAG_2_DC_30BIT_420 (0x01) 711 uint8_t byDataLength : 5;
712 uint8_t byTagCode : 3;
713 uint8_t abyIEEE_OUI[3];
715 uint8_t byMaxTMDSCharacterRate;
721 const uint8_t g_abyHDMI_VSDB[3] = { 0x03, 0x0C, 0x00 };
724 uint8_t byDataLength : 5;
725 uint8_t byTagCode : 3;
726 uint8_t abyIEEE_OUI[3];
730 uint8_t byMaxTMDSClockFreq;
732 uint8_t byVideoLatency;
733 uint8_t byAudioLatency;
734 uint8_t byInterlacedVideoLatency;
735 uint8_t byInterlacedAudioLatency;
737 uint8_t byHDMI3DLen : 4;
738 uint8_t byHDMIVICLen : 4;