Questa Design Coverage

Scope: /register_file_tb/DUT


Coverage Summary By Instance:

ScopeTOTALStatementBranchToggle
TOTAL98.94%100.00%100.00%96.83%
DUT98.94%100.00%100.00%96.83%

Local Instance Coverage Details:

Total Coverage:96.84%98.94%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Statements6601100.00%100.00%
Branches3301100.00%100.00%
Toggles2052198765196.83%96.83%

Recursive Hierarchical Coverage Details:

Total Coverage:96.84%98.94%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Statements6601100.00%100.00%
Branches3301100.00%100.00%
Toggles2052198765196.83%96.83%

Scope Details:

Instance Path:
/register_file_tb/DUT
Design Unit Name:
work.register_file
Language:
SystemVerilog
Source File:
testbench/register_file_tb.sv