Questa Design Unit Coverage

Design Unit: work.test


Design Unit Coverage Details:

Total Coverage:100.00%100.00%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Statements454501100.00%100.00%
Toggles2201100.00%100.00%

Scope Details:

Design Unit Name:
work.test
Language:
SystemVerilog
Source File:
testbench/alu_tb.sv