Questa
Design Unit Coverage
Design Unit: work.register_file_tb
Design Unit Coverage Details:
Total Coverage:
96.87%
87.50%
Coverage Type
Bins
Hits
Misses
Weight
% Hit
Coverage
Statements
28
28
0
1
100.00%
100.00%
Toggles
4
3
1
1
75.00%
75.00%
Scope Details:
Design Unit Name:
work.register_file_tb
Language:
SystemVerilog
Source File:
testbench/register_file_tb.sv