Questa Design Coverage

Scope: /alu_tb


Coverage Summary By Instance:

ScopeTOTALStatementBranchFEC
Condition
Toggle
TOTAL75.75%100.00%86.36%16.66%100.00%
alu_tb100.00%100.00%----100.00%
aluif100.00%------100.00%
PROG100.00%100.00%----100.00%
DUT67.67%100.00%86.36%16.66%--

Local Instance Coverage Details:

Total Coverage:100.00%100.00%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Statements2201100.00%100.00%
Toggles2201100.00%100.00%

Recursive Hierarchical Coverage Details:

Total Coverage:95.95%75.75%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Statements757501100.00%100.00%
Branches22193186.36%86.36%
FEC Conditions12210116.66%16.66%
Toggles21221201100.00%100.00%

Scope Details:

Instance Path:
/alu_tb
Design Unit Name:
work.alu_tb
Language:
SystemVerilog
Source File:
testbench/alu_tb.sv