Questa
Design Unit Coverage
Design Unit: work.alu_tb
Design Unit Coverage Details:
Total Coverage:
100.00%
100.00%
Coverage Type
Bins
Hits
Misses
Weight
% Hit
Coverage
Statements
2
2
0
1
100.00%
100.00%
Toggles
2
2
0
1
100.00%
100.00%
Scope Details:
Design Unit Name:
work.alu_tb
Language:
SystemVerilog
Source File:
testbench/alu_tb.sv