Questa Design Coverage

Scope: /register_file_tb


Coverage Summary By Instance:

ScopeTOTALStatementBranchToggle
TOTAL99.02%100.00%100.00%97.06%
register_file_tb87.50%100.00%--75.00%
writeAndRead100.00%100.00%----
rfif100.00%----100.00%
PROG87.50%100.00%--75.00%
DUT98.94%100.00%100.00%96.83%

Local Instance Coverage Details:

Total Coverage:96.87%87.50%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Statements282801100.00%100.00%
Toggles431175.00%75.00%

Recursive Hierarchical Coverage Details:

Total Coverage:97.12%99.02%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Statements424201100.00%100.00%
Branches3301100.00%100.00%
Toggles2284221767197.06%97.06%

Scope Details:

Instance Path:
/register_file_tb
Design Unit Name:
work.register_file_tb
Language:
SystemVerilog
Source File:
testbench/register_file_tb.sv