Questa Design Coverage

Scope: /register_file_tb/PROG


Coverage Summary By Instance:

ScopeTOTALStatementToggle
TOTAL87.50%100.00%75.00%
PROG87.50%100.00%75.00%

Local Instance Coverage Details:

Total Coverage:91.66%87.50%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Statements8801100.00%100.00%
Toggles431175.00%75.00%

Recursive Hierarchical Coverage Details:

Total Coverage:91.66%87.50%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Statements8801100.00%100.00%
Toggles431175.00%75.00%

Scope Details:

Instance Path:
/register_file_tb/PROG
Design Unit Name:
work.test
Language:
SystemVerilog
Source File:
testbench/register_file_tb.sv