Questa Design Unit Coverage

Design Unit: work.register_file_if


Design Unit Coverage Details:

Total Coverage:100.00%100.00%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Toggles22422401100.00%100.00%

Scope Details:

Design Unit Name:
work.register_file_if
Language:
SystemVerilog
Source File:
include/register_file_if.vh