Questa
Design Unit Coverage
Design Unit: work.register_file
Design Unit Coverage Details:
Total Coverage:
96.84%
98.94%
Coverage Type
Bins
Hits
Misses
Weight
% Hit
Coverage
Statements
6
6
0
1
100.00%
100.00%
Branches
3
3
0
1
100.00%
100.00%
Toggles
2052
1987
65
1
96.83%
96.83%
Scope Details:
Design Unit Name:
work.register_file
Language:
SystemVerilog
Source File:
source/register_file.sv