Questa
Design Unit Coverage
Design Unit: work.register_file_if
Design Unit Coverage Details:
Total Coverage:
100.00%
100.00%
Coverage Type
Bins
Hits
Misses
Weight
% Hit
Coverage
Toggles
224
224
0
1
100.00%
100.00%
Scope Details:
Design Unit Name:
work.register_file_if
Language:
SystemVerilog
Source File:
include/register_file_if.vh