Questa Design Unit Coverage

Design Unit: work.register_file


Design Unit Coverage Details:

Total Coverage:96.84%98.94%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Statements6601100.00%100.00%
Branches3301100.00%100.00%
Toggles2052198765196.83%96.83%

Scope Details:

Design Unit Name:
work.register_file
Language:
SystemVerilog
Source File:
source/register_file.sv