Questa
Design Coverage
Scope: /
work.register_file_tb
/
writeAndRead
Local Instance Coverage Details:
Total Coverage:
100.00%
100.00%
Coverage Type
Bins
Hits
Misses
Weight
% Hit
Coverage
Statements
26
26
0
1
100.00%
100.00%
Scope Details:
Instance Path:
/work.register_file_tb/writeAndRead
Language:
SystemVerilog
Source File:
testbench/register_file_tb.sv