Questa Design Coverage

Scope: /alu_tb/DUT


Coverage Summary By Instance:

ScopeTOTALStatementBranchFEC
Condition
TOTAL67.67%100.00%86.36%16.66%
DUT67.67%100.00%86.36%16.66%

Local Instance Coverage Details:

Total Coverage:79.03%67.67%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Statements282801100.00%100.00%
Branches22193186.36%86.36%
Conditions12210116.66%16.66%
UDP----------Excluded
FEC12210116.66%16.66%

Recursive Hierarchical Coverage Details:

Total Coverage:79.03%67.67%
Coverage TypeBinsHitsMissesWeight% HitCoverage
Statements282801100.00%100.00%
Branches22193186.36%86.36%
Conditions12210116.66%16.66%
UDP----------Excluded
FEC12210116.66%16.66%

Scope Details:

Instance Path:
/alu_tb/DUT
Design Unit Name:
work.alu
Language:
SystemVerilog
Source File:
testbench/alu_tb.sv