#Build: Synplify Pro (R) M-2017.03L-SP1-1, Build 086R, Aug 4 2017 #install: C:\lscc\diamond\3.10_x64\synpbase #OS: Windows 8 6.2 #Hostname: MEHRDAD-HP-WIN # Fri Apr 5 11:20:52 2019 #Implementation: syn_results Synopsys HDL Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 @N: : | Running in 64-bit mode Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys Verilog Compiler, version comp2017q2p1, Build 190R, built Aug 4 2017 @N: : | Running in 64-bit mode Copyright (C) 1994-2017 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @I::"C:\lscc\diamond\3.10_x64\synpbase\lib\lucent\ecp5u.v" (library work) @I::"C:\lscc\diamond\3.10_x64\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\diamond\3.10_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\diamond\3.10_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\lscc\diamond\3.10_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\diamond\3.10_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\lscc\diamond\3.10_x64\cae_library\synthesis\verilog\ecp5u.v" (library work) @I::"C:\lscc\diamond\3.10_x64\cae_library\synthesis\verilog\pmi_def.v" (library work) @I::"C:\work\tinysdr_fpga_lora_tx\lora_tx_clarity\my_pll_64mhz\my_pll_64mhz.v" (library work) Verilog syntax check successful! File C:\work\tinysdr_fpga_lora_tx\lora_tx_clarity\my_pll_64mhz\my_pll_64mhz.v changed - recompiling Selecting top level module my_pll_64mhz @N:CG364 : ecp5u.v(757) | Synthesizing module VHI in library work. @N:CG364 : ecp5u.v(761) | Synthesizing module VLO in library work. @N:CG364 : ecp5u.v(1696) | Synthesizing module EHXPLLL in library work. @N:CG364 : ecp5u.v(1568) | Synthesizing module PLLREFCS in library work. @N:CG364 : my_pll_64mhz.v(8) | Synthesizing module my_pll_64mhz in library work. @W:CL168 : my_pll_64mhz.v(22) | Removing instance scuba_vhi_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 76MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Apr 5 11:20:54 2019 ###########################################################] Synopsys Netlist Linker, version comp2017q2p1, Build 190R, built Aug 4 2017 @N: : | Running in 64-bit mode File C:\work\tinysdr_fpga_lora_tx\lora_tx_clarity\my_pll_64mhz\syn_results\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Apr 5 11:20:54 2019 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Apr 5 11:20:54 2019 ###########################################################]