Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
m_lab7_soc|rst_controller_001|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
m_lab7_soc|rst_controller_001|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
m_lab7_soc|rst_controller_001 33 31 0 31 1 31 31 31 0 0 0 0 0
m_lab7_soc|rst_controller|alt_rst_req_sync_uq1 2 1 0 1 1 1 1 1 0 0 0 0 0
m_lab7_soc|rst_controller|alt_rst_sync_uq1 2 0 0 0 1 0 0 0 0 0 0 0 0
m_lab7_soc|rst_controller 33 31 0 31 2 31 31 31 0 0 0 0 0
m_lab7_soc|irq_mapper 2 32 2 32 32 32 32 32 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_007 38 0 0 0 37 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_006 38 0 0 0 37 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_005 38 0 0 0 37 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_004 38 0 0 0 37 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_003 38 0 0 0 37 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_002 38 0 0 0 37 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter_001 38 0 0 0 37 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter|error_adapter_0 38 1 2 1 37 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|avalon_st_adapter 38 0 0 0 37 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|crosser_003|clock_xer 121 0 0 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|crosser_003 123 2 0 2 117 2 2 2 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|crosser_002|clock_xer 121 0 0 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|crosser_002 123 2 0 2 117 2 2 2 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|crosser_001|clock_xer 121 0 0 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|crosser_001 123 2 0 2 117 2 2 2 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|crosser|clock_xer 121 0 0 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|crosser 123 2 0 2 117 2 2 2 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_mux_001|arb|adder 20 10 0 10 10 10 10 10 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_mux_001|arb 9 0 4 0 5 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_mux_001 583 0 0 0 121 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_mux|arb|adder 32 16 0 16 16 16 16 16 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_mux|arb 12 0 4 0 8 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_mux 931 0 0 0 124 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_demux_007 119 1 2 1 117 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_demux_006 119 1 2 1 117 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_demux_005 120 4 2 4 233 4 4 4 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_demux_004 119 1 2 1 117 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_demux_003 120 4 2 4 233 4 4 4 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_demux_002 120 4 2 4 233 4 4 4 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_demux_001 120 4 2 4 233 4 4 4 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|rsp_demux 120 4 2 4 233 4 4 4 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_007 119 0 2 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_006 119 0 2 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_005|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_005|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_005 235 0 0 0 118 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_004 119 0 2 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_003|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_003|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_003 235 0 0 0 118 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_002|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_002|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_002 235 0 0 0 118 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_001|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_001|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux_001 235 0 0 0 118 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux|arb|adder 8 2 0 2 4 2 2 2 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux|arb 6 0 1 0 2 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_mux 235 0 0 0 118 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_demux_001 123 25 2 25 581 25 25 25 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|cmd_demux 126 64 2 64 929 64 64 64 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_009|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_009 111 0 2 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_008|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_008 111 0 2 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_007|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_007 111 0 2 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_006|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_006 111 0 2 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_005|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_005 111 0 2 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_004|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_004 111 0 2 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_003|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_003 111 0 2 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_002|the_default_decode 0 8 0 8 8 8 8 8 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_002 111 0 2 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_001|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router_001 111 0 5 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router|the_default_decode 0 11 0 11 11 11 11 11 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|router 111 0 5 0 117 0 0 0 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|key_s1_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|key_s1_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|key_s1_agent 303 39 45 39 327 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|switch_s1_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|switch_s1_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|switch_s1_agent 303 39 45 39 327 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sdram_s1_agent_rdata_fifo 79 41 0 41 36 41 41 41 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sdram_s1_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sdram_s1_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sdram_s1_agent 303 39 45 39 327 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|led_s1_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|led_s1_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|led_s1_agent 303 39 45 39 327 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|onchip_memory2_0_s1_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|onchip_memory2_0_s1_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|onchip_memory2_0_s1_agent 303 39 45 39 327 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sdram_pll_pll_slave_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sdram_pll_pll_slave_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sdram_pll_pll_slave_agent 303 39 45 39 327 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_agent 303 39 45 39 327 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sysid_qsys_0_control_slave_agent_rsp_fifo 151 39 0 39 110 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sysid_qsys_0_control_slave_agent|uncompressor 45 1 0 1 43 1 1 1 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sysid_qsys_0_control_slave_agent 303 39 45 39 327 39 39 39 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|nios2_gen2_0_instruction_master_agent 191 37 85 37 143 37 37 37 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|nios2_gen2_0_data_master_agent 191 37 85 37 143 37 37 37 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|key_s1_translator 112 6 30 6 36 6 6 6 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|switch_s1_translator 112 6 30 6 36 6 6 6 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sdram_s1_translator 112 4 4 4 98 4 4 4 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|led_s1_translator 112 6 30 6 70 6 6 6 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|onchip_memory2_0_s1_translator 112 7 27 7 75 7 7 7 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sdram_pll_pll_slave_translator 112 6 27 6 70 6 6 6 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|nios2_gen2_0_debug_mem_slave_translator 112 5 20 5 82 5 5 5 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|sysid_qsys_0_control_slave_translator 112 6 28 6 35 6 6 6 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|nios2_gen2_0_instruction_master_translator 113 51 0 51 105 51 51 51 0 0 0 0 0
m_lab7_soc|mm_interconnect_0|nios2_gen2_0_data_master_translator 113 12 0 12 105 12 12 12 0 0 0 0 0
m_lab7_soc|mm_interconnect_0 361 0 0 0 296 0 0 0 0 0 0 0 0
m_lab7_soc|sysid_qsys_0 3 9 2 9 32 9 9 9 0 0 0 0 0
m_lab7_soc|switch 12 0 0 0 32 0 0 0 0 0 0 0 0
m_lab7_soc|sdram_pll|sd1 3 1 0 1 6 1 1 1 0 0 0 0 0
m_lab7_soc|sdram_pll|stdsync2|dffpipe3 3 0 0 0 1 0 0 0 0 0 0 0 0
m_lab7_soc|sdram_pll|stdsync2 3 0 0 0 1 0 0 0 0 0 0 0 0
m_lab7_soc|sdram_pll 38 30 30 30 34 30 30 30 0 0 0 0 0
m_lab7_soc|sdram|the_lab7_soc_sdram_input_efifo_module 66 0 0 0 66 0 0 0 0 0 0 0 0
m_lab7_soc|sdram 66 1 1 1 58 1 1 1 32 0 0 0 0
m_lab7_soc|onchip_memory2_0|the_altsyncram|auto_generated 41 0 0 0 32 0 0 0 0 0 0 0 0
m_lab7_soc|onchip_memory2_0 44 0 1 0 32 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_debug_slave_wrapper|the_lab7_soc_nios2_gen2_0_cpu_debug_slave_sysclk 43 0 0 0 48 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_debug_slave_wrapper|the_lab7_soc_nios2_gen2_0_cpu_debug_slave_tck 130 0 1 0 43 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_debug_slave_wrapper 123 0 0 0 50 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_ocimem|lab7_soc_nios2_gen2_0_cpu_ociram_sp_ram|the_altsyncram|auto_generated 47 0 0 0 32 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_ocimem|lab7_soc_nios2_gen2_0_cpu_ociram_sp_ram 47 0 0 0 32 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_ocimem 92 0 6 0 65 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_avalon_reg 48 0 29 0 68 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_im 54 38 51 38 47 38 38 38 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_pib 0 36 0 36 36 36 36 36 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_fifo|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc 5 0 0 0 5 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_fifo|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc 4 2 0 2 4 2 2 2 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_fifo|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt 3 0 0 0 2 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_fifo 115 0 65 0 36 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_dtrace|lab7_soc_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode 9 0 6 0 4 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_dtrace 114 0 103 0 72 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_itrace 24 17 22 17 53 17 17 17 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_dbrk 99 0 0 0 103 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_xbrk 65 5 62 5 6 5 5 5 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_break 51 36 6 36 71 36 36 36 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci_debug 50 1 30 1 7 1 1 1 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_nios2_oci 178 0 0 0 69 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|lab7_soc_nios2_gen2_0_cpu_register_bank_b|the_altsyncram|auto_generated 44 0 0 0 32 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|lab7_soc_nios2_gen2_0_cpu_register_bank_b 44 0 0 0 32 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|lab7_soc_nios2_gen2_0_cpu_register_bank_a|the_altsyncram|auto_generated 44 0 0 0 32 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|lab7_soc_nios2_gen2_0_cpu_register_bank_a 44 0 0 0 32 0 0 0 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu|the_lab7_soc_nios2_gen2_0_cpu_test_bench 321 3 287 3 33 3 3 3 0 0 0 0 0
m_lab7_soc|nios2_gen2_0|cpu 149 1 32 1 133 1 1 1 0 0 0 0 0
m_lab7_soc|nios2_gen2_0 149 0 0 0 131 0 0 0 0 0 0 0 0
m_lab7_soc|led 38 24 24 24 40 24 24 24 0 0 0 0 0
m_lab7_soc|key 8 0 0 0 32 0 0 0 0 0 0 0 0
m_lab7_soc 14 0 0 0 33 0 0 0 32 0 0 0 0